The invention relates generally to integrated circuits and more particularly to the fabrication of interconnection layers for memory cell arrays and peripheral circuitry.
Semiconductor memory systems are comprised of two basic elements: memory storage areas and memory control areas. DRAM (dynamic random access memory), for example, includes a memory cell array, which stores information, and peripheral circuitry, which controls the operation of the memory cell array.
Interconnecting memory cell arrays and peripheral circuitry is of special concern in DRAM memory circuits; therefore, the invention will be discussed in connection with DRAM memory circuits. However, the invention has broader applicability and is not limited to DRAM memory circuits. It may be used in any other type of memory circuit, such as SRAM (static random access memory), in which memory storage areas and memory control areas are interconnected.
FIG. 1 is a block diagram of a DRAM. Referring to FIG. 1, DRAM 50 comprises: a memory cell array 51 for storing data signals of memory information; a row and column address buffer 52 for receiving external address signals for selecting a memory cell (constituting a unit memory circuit); a row decoder 53 and a column decoder 54 for designating the memory cell by decoding the address signals; a sense refresh amplifier 55 for amplifying and reading a signal stored in the designated memory cell; a data in buffer 56 and a data out buffer 57 for inputting/outputting data; and a clock generator 58 for generating a clock signal.
The peripheral circuitry communicates with and controls the storage operations of the memory cell array through interconnection layers (or interconnects) usually formed from aluminum or other metal. Typically, five or more metal interconnection layers are used. The fabrication of each metal interconnection layer typically requires several processing steps, including the deposition of an insulating layer, the formation of contacts, and the deposition of the interconnection material. Each of these processing steps in turn typically requires several masking and etching steps.
Because the formation of metal interconnection layers is complex and expensive, there is presently a need for structures and methods which reduce the overall number of metal interconnection layers required in the formation of semiconductor memory devices.
A semiconductor memory device in accordance with the invention includes a memory cell array having a plurality of memory cells each formed of at least one MOS transistor and at least one capacitor. Further, the memory device includes a peripheral circuit for writing/reading prescribed information to and from the memory cell region. The present invention reduces the number of steps necessary to manufacture semiconductor memory devices by providing a semiconductor structure and method in which the capacitor upper and lower electrode layers of the memory cell array are deposited within the peripheral circuitry as the first and second interconnection layers of the peripheral circuitry.
In accordance with the preferred embodiment of the invention, the first and second electrode layers are preferably deposited simultaneously within the memory cell array and the peripheral circuitry. Further in accordance with the preferred embodiment of the invention, the first and second electrode layers are preferably formed of the same material. Thus, the number of material layers, mask count and process steps required for memory fabrication are reduced.
These and other aspects, features and advantages of the invention will become apparent from the following detailed description of preferred embodiments of the present invention.